Dynamic random access memory (DRAM) may be utilized for storing information in programmable systems. DRAM may be fabricated as an array comprising individual memory cells containing a transistor in combination with a charge-storage device (such as, for example, a capacitor). Bitlines and wordlines may extend across the array, and may be utilized for accessing individual memory cells.
A continuing goal is to increase integration, and accordingly to increase packing density of DRAM and other circuitry. A problem encountered as DRAM is packed to higher density is that crosstalk between adjacent wordlines (sometimes referred to as a row-hammer) becomes increasingly problematic.
It is desired to develop new architectures suitable for fabrication of highly-integrated DRAM. It is further desired that such architectures alleviate or prevent problematic crosstalk between adjacent wordlines.